Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array

Abstract

With the increasing gap between processing speed and memory bandwidth necessity for in/near-memory computing has emerged, to ensure high-performance, energy-efficient computing for data-intensive applications at the edge. This work proposes a feasible SRAM compute cache with a sense amplifier (SA) based approach to perform in-/near memory Boolean computations with a novel reconfigurable assist sense amplifier (RASA). The RASA exploits assist transistors to achieve NAND, NOR and XNOR operations without affecting the transparency of normal read leading to fast and reliable sensing with only one SA. This effectively eliminates the need for two SAs in comparison to state-of-the-art solutions. The proposed work improves memory density and reduces cost-per-bit by leveraging the SA-based approach because existing solutions lead to significant area overhead/cell which reflects overhead multiply by the number of cells/column. The RASA provides flexibility to accommodate more cells per column at the architecture level. Extensive Monte-Carlo analysis is performed to verify the feasibility of the proposed circuit in commercial 65nm UMC technology under iso-SA area and iso-yield conditions. Simulations indicate a 34.34%, 84.87%, 81.21%, 75.46% improvement in energy, and a 71.30%, 43.36%, 32.49%, 17.44% improvement in throughput leading to a reduction of 60.97%, 91.37%, 87.22%, 79.62% in energy-delay product with respect to CLSA (Dong et al., 2018), CSRAM (Chen et al., 2021), RRCSA (Rajput et al., 2022) and the ADSA (Agrawal et al., 2018) respectively. An improvement in the area of SA by 36.512% is achieved with respect to RRCSA.