Building a RISC-V Processor

Bernard Goossens

doi:10.1007/978-3-031-18023-1_6

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Building a RISC-V Processor

Bernard Goossens

Year: 2023 Undergraduate topics in computer science Pages: 183-200

DOI: 10.1007/978-3-031-18023-1_6

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Keywords:

Microarchitecture Reduced instruction set computing Computer science Instructions per cycle Fetch Decoding methods Parallel computing Computer architecture Embedded system Instruction set ARM architecture Computer hardware Telecommunications Central processing unit

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Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Building a RISC-V Processor

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