A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable Platforms

Abstract

The dynamic partial reconfiguration (DPR) feature offered by modern FPGAs provides the flexibility of adapting the underlying hardware according to the needs of a particular situation at runtime, in response to application requirements. In recent times, DPR along with drastically reduced reconfiguration overheads has allowed the possibility of scheduling multiple real-time applications on FPGA platforms. However, in order to effectively harness the computation capacity of an FPGA floor, efficient techniques which can schedule real-time applications over both space and time are required. It may be noted that safety-critical systems often require resource-optimal solutions to reduce size, weight, cost and power consumption of the system. However, the scheduling of real-time tasks on FPGAs in the presence of non-negligible reconfigurationlcontext-switching overheads requires careful exploration of the state space which often makes it prohibitively expensive to be applied on-line. Hence, off-line formal approaches are often preferred in the design of reconfiguration controllers (i.e., schedulers) that are correct-by-construction as well as optimal in terms of usage of resources. In this paper, we propose a formal scheduler synthesis framework that generates an optimal scheduler for a set of non-preemptive periodic real-time tasks executing on a FPGA platform. We show the practical viability of our proposed framework by synthesizing schedulers for real-world benchmark applications and implementing them on FPGAs.