Hardware Design and Implementation of Post-Quantum Cryptography Kyber

Abstract

In order to resist quantum attacks, post-quantum cryptographic algorithms have become the focus of cryptog-raphy research. As a lattice-based key algorithm, the Kyber protocol has great advantages in the selection of post-quantum algorithms. This paper proposes an efficient hardware design scheme for Kyber512 whose security level is Ll. This paper first design a general hash module to reuse computing cores to improve resource utilization. A ping-pong RAM and a pipeline structure is used to design a general-purpose NTT processor to support all operations on polynomial multiplication. Finally, the inter-module cooperation and data scheduling are compactly designed to shorten the working cycle. In this paper, the top-level key generation, public key encryption and private key decryption modules are implemented on Artix 7 FPGA with 204MHz frequency. The times of the corresponding modules are 11.5s, 17.3s, and 23.5s, respectively. Compared with the leading hardware implementation, the design in this paper reduces the area-delay product by 10.2 %, achieving an effective balance between resources and area.