Reconfigurable Multicore Architectures for Streaming Applications

Abstract

This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) platforms for streaming digital signal processing applications, also called streaming DSP applications. In streaming DSP applications, computations can be specified as a data flow graph with streams of data items (the edges) flowing between computation kernels (the nodes). Most signal processing applications can be naturally expressed in this modeling style [14]. Typical examples of streaming DSP applications are wireless baseband processing, multimedia processing, medical image processing, sensor processing (e.g., for remote surveillance cameras), and phased array radars. In a heterogeneous multicore architecture, a core can either be a bit-level reconfigurable unit (e.g., FPGA), a word-level reconfigurable unit, or a general-purpose programmable unit (digital signal processor (DSP) or general purpose processor (GPP)). We assume the cores of the SoC are interconnected by a reconfigurable network-on-chip (NoC). The programmability of the individual cores enables the system to be targeted at multiple application domains.