Process Technology For Next Generation Photomask

Abstract

Due to the nonlinearity of print down from mask to wafer, mask error budget will be more tightened than shrinkage of design rule in SIA road map (Table l). Considering limitations and future directions to achieve the required SIA mask specifications, the advanced process technology for mask making must be developed now. In this paper, we will mainly discuss about the required photomask process to meet the CD uniformity less than 13nm in 0.13 μ m device generation and also important mask parameters such as pattern fidelity of submicron feature in mask, feature size control, throughput and other related issues will be discussed.