A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264

Abstract

We describe a fast VLSI architecture for full-search motion estimation for the blocks with 7 different sizes in MPEG-4 AVC/H.264. The proposed variable block size motion estimation (VBSME) architecture consists of a 16/spl times/16 PE array, an adder tree and comparators to find all 41 motion vectors and their minimum SADs for the blocks of 16/spl times/16, 16/spl times/8, 8/spl times/16, 8/spl times/8, 8/spl times/4, 4/spl times/8 and 4/spl times/4. It employs a 2D datapath and its control of the search area data is simple and regular. The proposed VBSME can achieve 100% PE utilization by employing a preload register and a search data buffer inside each PE and allow real-time processing of 4CIF(704/spl times/576) video with 15 fps at 100 MHz for a search range of |-32/spl sim/+31|.