JOURNAL ARTICLE

Data buffering: run-time versus compile-time support

Abstract

Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local processor memory (e.g. registers). This paper focuses solely on methods of increasing the utilization of data memory, local to the processor (registers or register-oriented buffers).

Keywords:
Computer science Cache-only memory architecture Interleaved memory Parallel computing Cache Compile time Processor register Memory management Uniform memory access Non-uniform memory access Physical address CPU cache Access time Register allocation Registered memory Semiconductor memory Operating system Memory address Compiler

Metrics

4
Cited By
1.34
FWCI (Field Weighted Citation Impact)
8
Refs
0.82
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Topics

Parallel Computing and Optimization Techniques
Physical Sciences →  Computer Science →  Hardware and Architecture
Embedded Systems Design Techniques
Physical Sciences →  Computer Science →  Hardware and Architecture
Interconnection Networks and Systems
Physical Sciences →  Computer Science →  Computer Networks and Communications
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