JOURNAL ARTICLE

A performance driven macro-cell placement algorithm

Tong GaoP.M. VaidyaC.L. Liu

Year: 2003 Journal:   [1992] Proceedings 29th ACM/IEEE Design Automation Conference Pages: 147-152

Abstract

The authors present a new performance driven macro-cell placement algorithm. Placement of modules is guided by a set of upper- and lower-bounds on the net wire lengths. A convex programming algorithm is used to compute a set of upper-bounds on the net wire lengths which will ensure that timing requirements between input and output signals are satisfied. A set of lower-bounds is also computed to control signal skews at intermediate points of the circuit. Artificial nets are introduced between all pairs of modules. Lower-bounds on the lengths of the artificial nets are computed to avoid module overlaps in the placement. A modified min-cut placement algorithm is then used to generate a placement that satisfies the upper- and lower-bounds. An iterative procedure is used to modify the set of upper- and lower-bounds to improve the quality of the placement result. Experimental results on eight test examples are included.< >

Keywords:
Upper and lower bounds Set (abstract data type) Algorithm Macro Placement Computer science Iterative refinement Regular polygon Mathematics Mathematical optimization Circuit design Physical design

Metrics

32
Cited By
2.74
FWCI (Field Weighted Citation Impact)
14
Refs
0.90
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

VLSI and FPGA Design Techniques
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Low-power high-performance VLSI design
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
VLSI and Analog Circuit Testing
Physical Sciences →  Computer Science →  Hardware and Architecture

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