JOURNAL ARTICLE
Wafer-Level LICCDM Device Testing
Abstract
With the integrated circuit technology evolution towards 25D and 3D stacking, wafer-level and bare-die-level electrostatic discharge testing is becoming a necessity. In this work, we use our Low-Impedance Contact CDM tester to measure integrated circuit products and assess the possibilities and potential issues of CDM testing of wafers and bare dies.
Keywords:
Wafer Stacking Electrostatic discharge Wafer testing Wafer-level packaging Electrical impedance Die (integrated circuit) Integrated circuit Materials science Electronic engineering Engineering Electrical engineering Mechanical engineering Optoelectronics Voltage Physics
Metrics
2
Cited By
0.18
FWCI (Field Weighted Citation Impact)
15
Refs
0.52
Citation Normalized Percentile
Is in top 1%
Is in top 10%
Citation History
Topics
Electrostatic Discharge in Electronics
Physical Sciences → Engineering → Electrical and Electronic Engineering
Integrated Circuits and Semiconductor Failure Analysis
Physical Sciences → Engineering → Electrical and Electronic Engineering
Physical Unclonable Functions (PUFs) and Hardware Security
Physical Sciences → Computer Science → Hardware and Architecture
Related Documents
JOURNAL ARTICLE
Fabrication and Testing of a Wafer-Level Vacuum Package for MEMS Device
C.S. PremachandranSer Choong ChongSaxon LiwRanganathan Nagarajan
Journal: IEEE Transactions on Advanced Packaging Year: 2009 Vol: 32 (2)Pages: 486-490
JOURNAL ARTICLE
WCDM2 — Wafer-level charged device model testing with high repeatability
Nathan JackTimothy J. MaloneyBruce C. S. ChouElyse Rosenbaum
Year: 2011 Pages: 4C.5.1-4C.5.8
JOURNAL ARTICLE
Design, Fabrication and Testing of Wafer Level Vacuum Package for MEMS Device
C.S. PremachandranSer Choong ChongS. LiwR. Nagarajan
Year: 2006 Pages: 1136-1140
JOURNAL ARTICLE
Wafer-Level Testing Challenge for Flip Chip and Wafer-Level Packages
Journal: Wafer-Level Packaging Symposium Year: 2012 Vol: 9 (1)