Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions
Philippos PapaphilippouKelly Paul H. J.Wayne Luk
Abstract
Simodense is a high-performance open-source RISC-V (RV32IM) softcore, optimised for exploring custom SIMD instructions. In order to maximise SIMD instruction performance, the design’s memory system is optimised for streaming bandwidth, such as very wide blocks for the last-level cache. The approach is demonstrated on example memory-intensive applications with custom instructions. This paper also provides insights on the effectiveness of adding FPGA resources in general purpose processors in the form of reconfigurable SIMD instructions.
Metrics
Citation History
Topics
Related Documents
Demonstrating custom SIMD instruction development for a RISC-V softcore
Philippos PapaphilippouPaul H. J. KellyWayne Luk
RISC-V SIMD Instructions - Vector Extension (Load/Store)
B KavyashreeA GeethashreeSuresh MuthusamyNiranjan Khatavkar RD D SuhasN M Nikhil
Implementation and Evaluation of SIMD Instructions using RISC-V
Adaptive Gradual Quantization with a Custom RISC-V SIMD Accelerator
Zongcheng YueDongwei YanSean Longyu MaChiu-Wing Sham
Labidus: RISC-V Overlay with Streaming Asynchronous Custom Instructions
Gongjin SunSeongyoung KangJijiang HeSe-Min LimSang-Woo Jun