JOURNAL ARTICLE

BIST Based Aging Fault Prediction Using Machine Learning

S PrashanthR SuchetaR. VishvaGanesh Kumar T RNavya Mohan

Year: 2021 Journal:   2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC) Pages: 1715-1722

Abstract

With the rapid reduction in the size of chips nowadays, the phenomenon of circuit aging is becoming more significant. The impact of circuit aging includes slower chip speed, irregular timing characteristics, and increased power consumption. Such impacts have a negative effect on the proper functioning of the chips. Instead of over-designing chips to ensure reliable operation for a long time, this research work proposes a system to monitor the aging process and determine the stage of aging the chip so that, the necessary corrective measures can be undertaken to avoid any functional failures that may occur over time.

Keywords:
Computer science Power consumption Chip Process (computing) Fault (geology) Reliability engineering Reduction (mathematics) Power (physics) Embedded system Engineering

Metrics

3
Cited By
0.31
FWCI (Field Weighted Citation Impact)
29
Refs
0.39
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

VLSI and Analog Circuit Testing
Physical Sciences →  Computer Science →  Hardware and Architecture
Advancements in Semiconductor Devices and Circuit Design
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Semiconductor materials and devices
Physical Sciences →  Engineering →  Electrical and Electronic Engineering

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