Design of Convolution Neural Network Accelerator Based on FPGA

Abstract

In this paper, aiming at the embedded and realtime target detection platform, from the perspective of highspeed hardware implementation, the target detection algorithm based on Mobilenet-SSD is analyzed. The CNN accelerator based on FPGA is designed, using hardware optimization techniques such as parallel, pipelining and double buffering. The function verification and performance test are carried out on GVI Cxz7100 development board. The test results show that the design function is correct, and the processing speed is better than that of PC.