Simulation Study of Process Variations in Double Gate Junctionless Field-Effect Transistors

Abstract

This work discusses the process variations in symmetrical double-gate (DG) junctionless (JL) field-effect transistors (FETs) by device simulation. Output I-V characteristics along with subthreshold slope increase, DIBL variations with drain voltage and threshold voltage shift variations are systematically analyzed with the general variability issues including oxide thickness, channel thickness and doping concentration. Potential distribution in the body channel region is also analyzed. Optimum values of the variability factors are considered to obtain the characteristics of the proposed MOSFET. Comparison with Double Gate inversion mode (IM) FETs have been done for some process variation parameters to highlight the advantages of JL FETs. Cogenda’s Visual TCAD tool has been used for the device simulation and parameter extraction