Low‐Power Computing with Neuromorphic Engineering

Abstract

The increasing power consumption in the existing computation architecture presents grand challenges for the performance and reliability of very‐large‐scale integrated circuits. Inspired by the characteristics of the human brain for processing complicated tasks with low power, neuromorphic computing is intensively investigated for decreasing power consumption and enriching computation functions. Hardware implementation of neuromorphic computing with emerging devices substantially reduces power consumption down to a few mW cm −2 , compared with the central processing unit based on conventional Si complementary metal–oxide semiconductor (CMOS) technologies (50–100 W cm −2 ). Herein, a brief introduction on the characteristics of neuromorphic computing is provided. Then, emerging devices for low‐power neuromorphic computing are overviewed, e.g., resistive random access memory with low power consumption (< pJ) per synaptic event. A few computation models for artificial neural networks (NNs), including spiking neural network (SNN) and deep neural network (DNN), which boost power efficiency by simplifying the computing procedure and minimizing memory access are discussed. A few examples for system‐level demonstration are described, such as mixed synchronous–asynchronous and reconfigurable convolution neuron network (CNN)–recurrent NN (RNN) for low‐power computing.