Access-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead

Abstract

The performance and energy penalties of DRAM refresh have increased in successive generations of higher capacity DRAM devices. This trend is likely to continue in future systems where the internal DRAM refresh cycle is opaque to the memory controller and the memory device oblivious of context. This paper presents Access-Aware Per-bank DRAM Refresh, a refresh control method that mitigates the negative impacts of refreshes, and its memory controller architecture. Novel capabilities are introduced in the memory controller. An access-aware refresh control unit analyses the short-term history of memory accesses translating row activations into refresh masks. Refresh masks are used either to skip rows, shortening the refresh cycle, or to completely omit refresh operations. The set of DRAM commands is extended with two new per-bank refresh commands that provide the memory controller not only an ability to omit refreshes, but also a context-rich fine-grained control of refresh operations. A proof of concept model of our architecture is implemented in a virtual platform where a set of applications is used to exercise the memory subsystem. Evaluations show that for the workloads considered the proposed architecture and refresh control method improve, either by reducing the latency or by completely omitting, up to 19% of the refresh operations.