45RFSOI WLCSP Board Level Package Risk Assessment and Solder Joint Reliability Performance Improvement

Abstract

The acceptance of Wafer Level Chip Scale Package (WLCSP) technology is significantly increasing for use in small devices such as mobile phones, wearable, RF antenna packages, and health monitor sensors. WLCSP structures can have a few thin redistribution layers (RDLs) between the chip surface and the printed circuit board (PCB), or the interconnectors can be placed in direction connection to the back end of the line (BEoL). Due to the high coefficient of thermal expansion (CTE) mismatch between the silicon chip and the organic laminate, the WLCSP chip's board level reliability (BLR) can present a significant challenge. In this paper, BLR tests applying different board trace and bump array designs are discussed for a 45nm RFSOI WLCSP package. A fatigue model is developed utilizing the BLR qualification tests and numerical simulation is then used to correlate the BLR experimental data. A newly improved test vehicle configuration was built based on learning from the BLR test and FEM learning. The result shows significantly improved solder joint lifetime when compared with the initial design.