3D-Stacked Memory For Shared-Memory Multithreaded Workloads

Abstract

This paper aims to address the issue of CPU-memory intercommunication latency with the help of 3D stacked memory.We propose a 3D-stacked memory configuration, where a DRAM module is mounted on top of the CPU to reduce latency.We have used a comprehensive simulation environment to assure both fabrication feasibility and energy efficiency of the proposed 3D stacked memory modules.We have evaluated our proposed architecture by running PARSEC 2.1, a benchmark suite for shared-memory multithreaded workloads.The results demonstrate an average of 40% improvement over conventional DDR3/4 memory architectures.