Abstract

In this paper, we propose a validation suite, applicable for different RISC-V designs. The suite can be considered as a stack of the following three layers: a framework based on MicroTESK TPG and formal specifications of RISC-V ISA, the test templates layer, and the test program layer. All these layers are closely connected, allowing to automatically receive basic tests for ISA. The suite has been applied for Syntacore's SCR1 core and ETH Zurich's RISCY core.

Keywords:
Suite Test suite Computer science Stack (abstract data type) Reduced instruction set computing Layer (electronics) Template Open source Operating system Programming language Test case Instruction set Software

Metrics

3
Cited By
0.34
FWCI (Field Weighted Citation Impact)
9
Refs
0.63
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

Radiation Effects in Electronics
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
VLSI and Analog Circuit Testing
Physical Sciences →  Computer Science →  Hardware and Architecture
Embedded Systems Design Techniques
Physical Sciences →  Computer Science →  Hardware and Architecture

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