Packaging Challenges and Reliability Performance of Compound Semiconductor Focal Plane Arrays

Abstract

The development of new high-performance Focal Plane Arrays (FPAs) for imaging systems is driven by advances in photodetector material growth and processing, readout integrated circuits and IR detector chip hybridisation/packaging. The hybridisation of the IR detector chip and the readout integrated circuit (ROIC) through flip-chip bonding is a key packaging challenge for pixel arrays with very small indium bumps and 10-30 m pitch sizes. This paper details the development and use of finite element models that can be used to assess and optimise the compression bonding process, and can enable insights into the impact of chip misalignment on the resulting flip-chip quality and the bonding equipment placement accuracy requirements for a given FPA specification. In addition, the fatigue performance of the indium interconnects of different fine pitch FPAs is evaluated and compared. The modelling results point that high quality interconnects and robust, defects-free assembly require micrometre placement accuracy. It is also possible that indium joints of higher resolution, larger size FPAs accumulate less damage under cryogenic temperature cycling compared to less dense, smaller in size, focal plane arrays.