Demonstration of InAs nanowire vertical transistors

Abstract

This paper reports on selective-area growth of vertical InAs/InAsP core-shell (CS) NWs on Si, and demonstration of vertical surrounding-gate transistors (SGTs) and InAs/InP CS NW-Si heterojunction TFET. NWs were grown by selective-area metalorganic vapor phase epitaxy (SA-MOVPE). The growth temperature was 550°C and III/V ratio was 256. Zn-pulsed doping layer was grown for 5 min, followed by Si-doped InAs growth for 3 min and growth of Sn-pulsed-doped layer for 5 min. Finally, InP shell was grown for 7 sec. As for InAsP layer, the P content in vapor phase was 40%. The SGT exhibits minimum subthreshold slope (SS) of 88 mV/decade at V _DS = 0.50 V and low leakage current (~ 10 ^-12 A/μm). ON-state current for the CS NW-channel was 2 times higher than bare InAs NW SGTs. This was assumed that the elastic strain due to lattice mismatch in CS layer was supperss electron scattering process. The TFET showed SS of 46 mV/decade which was below physical limitation of FET (60 mV/decade). The on/off ratio of 2 decade at V _DS = 0.50 V due to low source doping level. Further design of source region and shell structure will be discussed to enhance ON-state current.