JOURNAL ARTICLE

Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration

Abstract

State-of-the-art convolutional neural networks are enormously costly in both compute and memory, demanding massively parallel GPUs for execution. Such networks strain the computational capabilities and energy available to embedded and mobile processing platforms, restricting their use in many important applications. In this paper, we propose BCNN with Separable Filters (BCNNw/SF), which applies Singular Value Decomposition (SVD) on BCNN kernels to further reduce computational and storage complexity. We provide a closed form of the gradient over SVD to calculate the exact gradient with respect to every binarized weight in backward propagation. We verify BCNNw/SF on the MNIST, CIFAR-10, and SVHN datasets, and implement an accelerator for CIFAR10 on FPGA hardware. Our BCNNw/SF accelerator realizes memory savings of 17% and execution time reduction of 31.3% compared to BCNN with only minor accuracy sacrifices.

Keywords:
Computer science MNIST database Convolutional neural network Field-programmable gate array Singular value decomposition Hardware acceleration Acceleration Separable space Parallel computing Computational complexity theory Reduction (mathematics) Massively parallel Artificial neural network Filter (signal processing) State (computer science) Computer engineering Computer hardware Algorithm Artificial intelligence Computer vision Mathematics

Metrics

23
Cited By
2.03
FWCI (Field Weighted Citation Impact)
35
Refs
0.90
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

Advanced Neural Network Applications
Physical Sciences →  Computer Science →  Computer Vision and Pattern Recognition
Human Pose and Action Recognition
Physical Sciences →  Computer Science →  Computer Vision and Pattern Recognition
Image Enhancement Techniques
Physical Sciences →  Computer Science →  Computer Vision and Pattern Recognition

Related Documents

JOURNAL ARTICLE

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks

Jan B. SommerM. Akif ÖzkanOliver KeszöczeJürgen Teich

Journal:   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Year: 2022 Vol: 41 (11)Pages: 3767-3778
JOURNAL ARTICLE

Hardware Acceleration Schemes for Convolutional Neural Networks

Zhiqing XieJiang XueMeihua PengZiheng Yang

Journal:   Journal of Physics Conference Series Year: 2023 Vol: 2637 (1)Pages: 012013-012013
© 2026 ScienceGate Book Chapters — All rights reserved.