Ultra-Low Power Analog Multiplier Based on Translinear Principle

Abstract

In this paper, a wide dynamic range, current-mode four-quadrant analog multiplier circuit is proposed that utilizes MOS translinear principle. The proposed multiplier is designed in 65nm technology using CMOS transistors operating in weak inversion. A thorough analysis of the proposed design is performed using Spectre and monte-carlo simulations. The multiplier consumes a low power of 0.48μW and supports an input range of ±200nA while operating from 0.8V supply and exhibits an average total harmonic distortion (THD) 1.12%. Post layout simulation results show a high figure-of-merit (FoM) of 1302 verifying superiority of our design against other state-of-the-art multiplier circuits.