Anh H. NguyenMasashi AonoYuko Hara–Azumi
This study presents a hardware architecture design to solve the Satisfiability (SAT) problem which can represent various types of control applications in Cyber-Physical Systems (CPS). The proposed architecture adapts an emerging bio-inspired SAT solver, "AmoebaSAT" which possesses the high potentials of parallel computing and is thus suitable for hardware implementation. By exploring several hardware optimization techniques through an advanced high-level design technology (i.e., high-level synthesis), we realized an FPGA-based AmoebaSAT solver applicable to any CPS application whose control rules can be expressed as a SAT instance.
Masashi AonoSong-Ju KimLi ZhuMakoto NaruseMotoichi OhtsuHirokazu HoriMasahiko Hara
Kazuaki HaraNaoki TakeuchiMasashi AonoYuko Hara–Azumi
Naoki TakeuchiMasashi AonoYuko Hara-AzumiChristopher L. Ayala
Anh H. NguyenMasashi AonoYuko Hara–Azumi
Umara HanifMuhammad Naveed AmanBiplab Sikdar