Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction

Abstract

Due to few cells in memory that have shorter retention time, DRAM controller have to raise the refresh frequency to keep data integrity, and hence produce unnecessary refresh for the other normal cells, which result in large refresh overhead and the delay of memory access. In this paper, we propose an integration scheme to integrate retention-aware refresh and BISR techniques. Based on the RAAR method, our strategy can choose the most appropriate way of weak cell fixing to minimize the waste of non-weak row refresh. A dynamic programming algorithm with a state transition equation is proposed to resolve this problem. Experimental results show that with this BISR integration scheme, we can further reduce refresh power than without applying it.