FPGA Implementation of Energy Efficient Approximate Multiplier with Image Processing Applications

Abstract

Multiplication is the pivotal building squares in image processing, DSP applications. To make high-speed here using an approximate multiplier this is an efficient one. For that the method is to rounding the values of numbers to the nearest power of two. Using this method the complicated part of multiplication can be removed thus can improve the speed of multiplication. This multiplier is applicable for both positive and negative number. The efficiency of this multiplier is analysed by comparing with the accurate multipliers and finally studied its efficiency in image processing applications like image smoothening and sharpening. The multiplier operation is finally implemented in FPGA SPARTAN kit.