Abstract

Hardware implementation of Recurrent neural networks are able to increase the computing capacity in relation to software, so it can be of high interest when ultra-high speed processing is a requirement. However, the traditional hardware realization of neural networks has a cost in terms of power dissipation and circuit area due to the need of implementing a large quantity of binary multipliers as part of the synapses process. In this paper, a recurrent neural network scheme known as simple cyclic reservoir is implemented for time series processing. Synapses are implemented using single shift-add operations that maintains a similar accuracy with respect to full multipliers but with high savings in terms of area and power. The network architecture takes advantage of the fixed connectivity of the reservoir that only modifies the output layer of the network. Such design is synthesized in a digital circuitry, evaluated for a time-series benchmark prediction task and compared with previously published hardware implementation of a Reservoir Computing systems.

Keywords:
Computer science Reservoir computing Benchmark (surveying) Artificial neural network Process (computing) Realization (probability) Field-programmable gate array Binary number Task (project management) Computer hardware Recurrent neural network Computer architecture Real-time computing Embedded system Artificial intelligence Arithmetic Engineering

Metrics

11
Cited By
0.60
FWCI (Field Weighted Citation Impact)
37
Refs
0.73
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

Neural Networks and Reservoir Computing
Physical Sciences →  Computer Science →  Artificial Intelligence
Advanced Memory and Neural Computing
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Neural dynamics and brain function
Life Sciences →  Neuroscience →  Cognitive Neuroscience

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