An automatic parallelizer for Coarse-Grained Reconfigurable processor

Abstract

Coarse-Grained Reconfigurable Architectures (CGRA) can accelerate computing speed with high power efficiency. Based on its special architecture, a corresponding compiler is designed to map the applications onto CGRAs. In order to exploit its parallelism, we design an automatic parallelizer for the compiler. This tool is aimed to transform source code to target code with multiple sub-functions, which has significant impact on the computing performance. In this paper, an algorithm is developed for code transformation and a parallel scheduling policy is applied. Our experiments show that this module can improve the computing performance.