Energy-aware scheduling for task adaptive FPGAs

Abstract

In this paper, we present a design time tool, EASTA, that combines reconfigurability in FPGAs and Dynamic Frequency Scaling to realize an efficient multiprocessing architecture on a single-FPGA system. Multiple deadlines, re-convergent nodes, flow dependency and processor constraints of the multi-processor problem on a general task graph are rigorously taken into consideration. EASTA is able to determine the minimum number of PEs required to create a feasible schedule, represented in an efficient tree-based table, and dynamically adjust the clock speed of each processing element to reclaim slack. Energy savings of approximately 32% are obtained for a sample task graph.