Variable-length VLIW encoding for code size reduction in embedded processors

Abstract

Very-long-instruction-word (VLIW) architectures are widely adopted in high-performance and low-power digital signal processors (DSP) due to their simplicity from extensive software optimizations. However, their poor code density (usually > 2× code size for a given application) and corresponding instruction accesses can overwhelm the energy savings on DSP datapaths. This paper presents variable-length VLIW (VL ² IW), where the unused condition codes, operands/operand scope, and reduced range of immediate variables of TI C64x+ DSP are exploited to improve the code density. The static grouping and run-time dispersal schemes of the variable-length instructions in a VLIW packet are described. In our experiments, 21% code sizes are saved in average for MiBench kernels. The hardware overhead is only ~5%.