Electret-free electrostatic energy harvesting interface circuit design and analysis

Abstract

In this paper, electrostatic energy harvesting interface circuit is introduced and analyzed. The harvester and interface circuit are designed using GF 65nm process technology and cadence CAD tools. System level analysis is performed where the impact of the initial voltage level and the harvester resonance frequency have been studied. Moreover, the maximum power that can be delivered to a resistive load using the harvester is presented. The efficiency of the interface circuit was shown to increase with higher resonance frequencies and initial voltage levels. As a result, however, the output voltage achieved by the harvesters was shown to exceed the tolerable voltage by CMOS technology. The proposed design includes a reconfigurable switch capacitor to reduce the electrostatic energy harvesting circuit voltage from 3V to 1.5V.