DHyANA: A NoC-based neural network hardware architecture

Abstract

Understanding and modeling the brain is one of the key scientific challenges in the twenty-first century, and a grown effort is rising on a global scale. Due to its high parallelism, the hardware implementation of large-scale spiking neural networks (SNNs) promises superior execution speed compared to sequential software approaches. Such systems can significantly benefit from the use of networks-on-chip(NoC), as they scale very well concerning area, performance, power/energy consumption, and overall design effort. We developed a hierarchical network-on-chip for a hardware SNN architecture to improve the communication and scalability of the system. The architecture was implemented in an Altera Stratix IV FPGA, and a logic synthesis was performed to evaluate the system, achieving an area of 0.23mm ² and a power dissipation of 147mW for a 256 neurons implementation.