A high parallel HEVC Fractional Motion Estimation architecture

Abstract

HEVC is the newest standard developed by the Joint Collaborative Team on Video Coding (JCT-VC). HEVC or H.265 includes several modifications compared with its predecessor the H.264/AVC, especially those involved in Fractional Motion Estimation (FME). This work is focused on the FME process that is an important part of an HEVC CODEC, because of its high computational complexity that demands a 40–60% of processing time of the whole coding process. On the basis of this feature and the real-time applications requirements, it is presented a high parallel hardware architecture for the HEVC FME process. The proposed architecture employs a simple hardware implementation for the Sum of Absolute Differences (SAD) in order to determine the best match block using fractional interpolated pixels. Additionally, the proposed architecture reuses the Interpolation unit for both half and quarter-pixel processes. The design was described using VHDL and synthesized to the Xilinx Virtex-4, Virtex-5, Virtex-6 and Virtex-7 FPGAs. The results established a maximum frequency of 97.65 MHz with capacity to process 55.55 frames per second (fps) for HDTV (1920×1080) video streams.