Decimal multiplication using compact BCD multiplier

Abstract

Decimal multiplication is an integral part offinancial,\ncommercial, and internet-based computations. The basic\nbuilding block of a decimal multiplier is a single digit\nmultiplier. It accepts two Binary Coded Decimal (BCD)\ninputs and gives a product in the range [0, 81] represented\nby two BCD digits. A novel design for single digit decimal\nmultiplication that reduces the critical path delay and area\nis proposed in this research. Out of the possible 256\ncombinations for the 8-bit input, only hundred\ncombinations are valid BCD inputs. In the hundred valid\ncombinations only four combinations require 4 x 4\nmultiplication, combinations need x multiplication,\nand the remaining combinations use either x or x\n3 multiplication. The proposed design makes use of this\nproperty. This design leads to more regular VLSI\nimplementation, and does not require special registers for\nstoring easy multiples. This is a fully parallel multiplier\nutilizing only combinational logic, and is extended to a\nHex/Decimal multiplier that gives either a decimal output\nor a binary output. The accumulation ofpartial products\ngenerated using single digit multipliers is done by an array\nof multi-operand BCD adders for an (n-digit x n-digit)\nmultiplication.