Compile-time instruction scheduling for superscalar processors

Abstract

Superscalar processors might be considered the next step in the evolution of uniprocessors beyond reduced-instruction-set computers (RISCs). The scheduling technology that is described could analogously be considered a major step in the evolution of optimizing compilers for uniprocessor architecture. A superscalar processor is a machine that can issue several instructions per cycle. To fully exploit a superscalar processor of degree n, there must be n instructions concurrently executing at all times. Should such parallelism not be available, stalls and dead time occur where instructions are forced to wait for the results of previous instructions. Thus, superscalar processor code must be carefully ordered to best utilize the inherent performance potential. Software schedulers are basically code reorganizers that increase performance by increasing available instruction parallelism. Given that a good scheduler can significantly improve the performance of compiled code, the superscalar approach becomes viable. The principles of scheduler technology based on the SF 960 scheduler developed by Quantitative Technology Corporation for the Intel i960CA superscalar processor are described.< >