High-radix parallel dividers for VLSI signal processing

Abstract

This paper presents a unified approach for designing high-radix dividers for on-line signal and data processing applications. It has long been recognized that the use of higher radices makes possible the reduction of computational steps in the division process. However most of the conventional high-radix algorithms are not suited for designing high-speed parallel dividers since they require lookup tables for selecting the quotient digits. We present a high-radix divider design that does not assume the use of lookup tables and is applicable to arbitrary radices. By prescaling the operands and converting the representation of each partial remainder into partially non-redundant representation, the quotient digit can be obtained directly from the integer part of the partial remainder. This paper also discusses the design of a radix-8 fully parallel divider as an example.