Abstract

A full-digital 12-channel, 100-step capacitive sensor is described. The capacitance to be sensed forms an RC-delay line whose delay is compared with that of a reference RC-delay line. The difference of the RC delays is sensed by a simple full-digital time-to-digital converter (TDC). By compensating the parasitic capacitance at power up, the capacitive sensor implemented in a 0.35 mum standard digital CMOS technology shows 30fF sensing resolution. The capacitive sensor consumes 5 muA per channel under 3.3V supply voltage.

Keywords:
Capacitive sensing CMOS Capacitance Parasitic capacitance Electrical engineering Electronic engineering Channel (broadcasting) Line (geometry) Computer science Engineering Physics Electrode

Metrics

3
Cited By
0.34
FWCI (Field Weighted Citation Impact)
7
Refs
0.69
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

Electrical and Bioimpedance Tomography
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Microfluidic and Bio-sensing Technologies
Physical Sciences →  Engineering →  Biomedical Engineering
Analytical Chemistry and Sensors
Physical Sciences →  Chemical Engineering →  Bioengineering

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