Front-end electronics for Silicon photo-multipliers coupled to fast scintillators

Abstract

As a result of a comprehensive study aimed at the development of integrated front-end electronics suitable for Silicon Photomultiplier detectors, a 32-channel self-triggered ASIC has been designed in a standard 0.35μm CMOS technology. Characterization measurements, carried out exploiting an external injection capacitance, demonstrate that the architecture of the analog channel, based on a full current-mode approach, allows to achieve very good performance in terms of dynamic range (around 70pC), bandwidth and timing accuracy (σ@118ps). The ASIC has been used in self-triggered mode to read-out a SiPM from Hamamatsu, coupled to a small LYSO scintillator, and the resulting spectra obtained by exposing the detector to different radiation sources confirm the effectiveness of our design approach. Eventually, some modifications to the architecture of the ASIC are proposed to improve its performance in the detection of low light levels and to enhance the effectiveness of the sparse read-out acquisition mode. These new features have been implemented in a further version of the ASIC, containing also an 8-bit, 20Ms/s embedded ADC designed on purpose, which has been already submitted for fabrication.