An optimized FPGA implementation based on scale invariant feature transform feature points detection

Abstract

Aiming at the characteristics of SIFT (Scale Invariant Feature Transform) algorithm which has large amount of calculation and can be highly paralleled, we propose an optimized FPGA implementation so that it can be accelerated on hardware. In this method, we firstly simplify the process of filtering image and generating Gaussian pyramids through selecting appropriate parameters and hardware structure, then use fixed-point decimals to increase the accuracy of operation, finally build feature detection module in a parallel way and make simulation and verification using different input images. Results of experiments show that, this method can significantly reduce the amount of calculation of the algorithm and save hardware resources with the premise of ensuring detection accuracy, which has a good performance.