A novel FPGA implementation of trellis shaping for PAPR reduction of OFDM signals

Abstract

In this paper, a novel hardware scheme of trellis shaping (TS) for PAPR reduction of OFDM signals is presented. A practical implementation of TS is challenging, and thus we demonstrate a possibility of its hardware implementation using FPGA. In particular, we focus on its hardware resource consumption and develop an approach to efficiently implement its functionality. The experimental results show that TS can be realized with a reasonable size of hardware resources based on the proposed approach on a Virtex-7 FPGA. Moreover, a trellis window truncation of TS that allows us to significantly reduce its computational complexity is also implemented in this paper, which enables an efficient PAPR reduction of 256-subcarrier OFDM signals with limited hardware resources.