Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture

Waqar Hussain; Henry Hoffmann; Tapani Ahonen; Jari Nurmi

doi:10.1007/s11265-016-1142-5

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Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture

Waqar Hussain Henry Hoffmann Tapani Ahonen Jari Nurmi

Year: 2016 Journal: Journal of Signal Processing Systems Vol: 87 (3)Pages: 287-297 Publisher: Springer Science+Business Media

DOI: 10.1007/s11265-016-1142-5

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Keywords:

Computer science Multi-core processor Reduced instruction set computing Parallel computing Instruction set Embedded system Synchronization (alternating current) Microarchitecture Computer architecture Frequency scaling Power (physics) Channel (broadcasting) Computer network

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Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture

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