Modelling and simulation of Si and InAs gate all around (GAA) nanowire transistors

Abstract

Owing to the large increase number of transistors in the CMOS logic due to the unending demand for increase in speed of electronic devices and also low power consumptions, it is becoming difficult to incorporate all the small scaled transistors onto one single plane. Nanowire transistors are now been looked upon to mitigate this particular problem due to their small size and excellent gate control all around the channel and hence the name GAA Nanowire. In this paper, simulation of Si and InAs GAA nanowire transistors is reported. This paper studies the band diagram of both along with their gate voltage and drain current dependencies. The current distribution along the channel has also been studied.