Microprocessor-Based Viterbi Decoding of Convolutional Codes

Abstract

For a short constraint length nonsystematic rate-half convolutional code with a Hamming distance of 5, a Viterbi decoding algorithm using Synertek—6502 microprocessor system has been developed. It has been shown here how the microprocessors can be interfaced to the coded signal from an external encoder and decode the data even in the presence of errors. The flowchart and the memory organization in the microprocessor have been discussed in this paper. Care has to be taken so that the calculated parameters, like the likelihood function does not exceed the word-length of the micro-processor. A throughput data rate of 2400 bps has been achieved with the system. This enables reliable transmission of 1200 bps data after encoding by rate-half error correction code to result in 2400 bps line rate, over telephone channels.It is important to consider the problems of requiring different computation time for different iterations in the decoding and establishing a reference time in the microprocessor to start iteration everytime. These problems have been solved by using the interrupt facilities.Errors have been added to the encoded output signal and the microprocessor-based Viterbi algorithm provided the decoded data correcting upto all patterns of 2 errors in 7 code bits. Experimental tests with random noise show that the decoder reduces the output error probability from 10-3 to 10-6.