Transparent Graphene Nanoplatelets for Charge Storage in Memory Devices

Abstract

Recently, graphene has been considered as a promising material for future low cost electronics because of its noteworthy properties, such as high carrier mobility, large work-function, thermal conductivity, structural robustness and optical transparency [1]. In this work, transparent graphene nanoplatelets are investigated for charge storage layers in low-cost non-volatile charge trapping memory devices. The memory electrical characterization, retention and endurance characteristics, and charge emission mechanism are analyzed. The memory cells are fabricated on an n + -type (111) (Antimony doped, 15-20 mµÙ-cm) Si wafer. 10-nm-thick Al 2 O 3 is deposited at 250 ° C in Cambridge Nanotech Savannah-100 atomic layer deposition (ALD) system. Pristine graphene nanoplatelets (NanoIntegris PureSheets Quattro grade) are deposited by drop-casting technique. Samples are placed on hot-plate at 110°C and 2-2.5 ml of 0.05 mg/ml graphene solution is drop-casted slowly by using plastic pipette and samples are left to dry for 5 minutes on hot-plate. Then a 5-nm-thick Al 2 O 3 tunnel oxide is ALD deposited at 250 ° C. A 400-nm-thick Al layer for the gate contact is sputtered using a shadow mask. A cross-sectional illustration of the fabricated memory device is depicted in Fig. 1a). Then, the memory devices are electrically characterized by measuring the C-V gate characteristics of the programmed and erased states at high frequency (1 MHz). Using the Agilent B1505A Semiconductor Device Parameter Analyzer, the memory cells gate voltage was first swept from -10 V forward to 10 V. The obtained C-V characteristic corresponds to the erased state as shown in Fig. 1b). Then, upon sweeping the gate voltage from +10 V to -10 V, there was a near parallel shift in the measured C-V curve in the positive direction as seen in Fig. 1b). The positive shift is due to electrons storage in the graphene nanoplatelets and the value of the V t shift is 4.4 V. The V t is extracted at a capacitance of 500 pF at the onset of the depletion region. The measured memory window at different operating voltages indicates a large V t shift (3.6 V) at low operating voltages (8/-8 V). At 10/-10 V, the charge trap states density of the graphene is calculated and found to be 5.83×10 12 cm -2 [2]. Furthermore, to identify the electron emission mechanism, the electric field across the tunnel oxide is calculated [3] and the natural logarithm of the V t shift divided by the square of the electric field is plotted vs. the reciprocal of the electric field as shown in Fig. 2. In Fowler-Nordheim tunneling (F-N), the charges are injected by tunneling into the conduction band of the oxide through a triangular energy barrier and then are swept by the electric field into the charge trapping layer. The emission rate of charges in F-N tunneling is exponentially proportional to the reciprocal of the electric field times the electric field squared [3]. Thus, the linear trend presented in Fig. 2 indicates that the dominating electron emission mechanism at electric fields larger than 5.6MV/cm (corresponding to a gate voltage of 6V) is F-N tunneling. Finally, the fabrication of such graphene based memory structure is compatible with existing semiconductor processing thus has potential on low-cost integrated nanoscale memory applications. Acknowledgment: This work was supported by ATIC, and TUBITAK Grants 109E044, 112M004, 112E052 and 113M815. References N. El-Atab, A. Ozcan, S. Alkis, A. K. Okyay, and A. Nayfeh "Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission", Appl. Phys. Lett. 104, 013112 (2014). F. Schwierz, Graphene transistors. Nat. Nanotechnol. 5, 487–496 (2010). S. M. SZE, “Nonvolatile Memory Devices,” in Physics of Semiconductor Devices , 3 rd ed. New Jersey: Wiley, 2007.