JOURNAL ARTICLE

Real-Time STAP demonstration on an embedded high performance computer

Mark LindermanRichard Linderman

Year: 1998 Journal:   IEEE Aerospace and Electronic Systems Magazine Vol: 13 (3)Pages: 15-31   Publisher: Institute of Electrical and Electronics Engineers

Abstract

Real-time signal processing for a 16-channel phased array radar, including space-time adaptive processing (STAP) algorithms, has been implemented using a 29-node ruggedized version of an Intel Paragon. Techniques employed to efficiently implement each step of the signal processing are discussed. An overall throughput of 3.15 GFLOPS and processing efficiency of 48% has been achieved, indicating that embedded high performance computers can deliver a significant percentage of their advertised peak throughput under real system constraints.

Keywords:
Space-time adaptive processing Throughput Computer science Signal processing Radar Real-time computing Computer hardware FLOPS Channel (broadcasting) Embedded system Digital signal processing Parallel computing Continuous-wave radar Telecommunications Radar imaging Wireless

Metrics

9
Cited By
0.87
FWCI (Field Weighted Citation Impact)
4
Refs
0.82
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

Radar Systems and Signal Processing
Physical Sciences →  Engineering →  Aerospace Engineering
Advanced SAR Imaging Techniques
Physical Sciences →  Engineering →  Aerospace Engineering
Antenna Design and Optimization
Physical Sciences →  Engineering →  Aerospace Engineering

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