Sampled charge reuse for power reduction in switched capacitor data converters

Abstract

A technique for reducing power dissipation in pipeline Analog-to-Digital converters (ADCs) is presented. The technique stems from the observation that the amplifier of a given stage is also expected to perform the sample and hold operation by charging the input capacitors of the subsequent stage. At the end of the amplification phase, the feedback capacitor of the first stage holds the residue voltage and it can be directly used as the input signal to the next stage thus eliminating the traditional need for charging an additional input capacitor. This capacitor reuse reduces the total capacitance that a given stage must drive thus reducing the power requirements for the operational amplifiers.