Instruction scheduling for the IBM RISC System/6000 processor

H. Shaw Warren

doi:10.1147/rd.341.0085

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JOURNAL ARTICLE

Instruction scheduling for the IBM RISC System/6000 processor

H. Shaw Warren

Year: 1990 Journal: IBM Journal of Research and Development Vol: 34 (1)Pages: 85-92 Publisher: IBM

DOI: 10.1147/rd.341.0085

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Abstract

For fast execution on the IBM RISC System/6000* processor, instructions should be arranged in an order that uses the arithmetic units as efficiently as possible. This paper describes the scheduling requirements of the machine, and a scheduling algorithm for it that is used in two compilers.

Keywords:

Computer science Reduced instruction set computing IBM Instruction scheduling Compiler Scheduling (production processes) Operating system Parallel computing Embedded system Schedule Instruction set Fair-share scheduling Two-level scheduling Engineering

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102

Cited By

15.15

FWCI (Field Weighted Citation Impact)

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0.99

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Is in top 1%

Is in top 10%

Citation History

Topics

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Numerical Methods and Algorithms

Physical Sciences → Computer Science → Computational Theory and Mathematics

Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Instruction scheduling for the IBM RISC System/6000 processor

Abstract

Metrics

Citation History

Topics

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