Memory-efficient and high-speed split-radix FFT/IFFT processor based on pipelined CORDIC rotations

Abstract

The author presents a CORDIC-based split-radix fast Fourier transform (FFT)/inverse FFT (IFFT) processor dedicated to the computation of 2048/4096/8192-point discrete Fourier transforms (DFTs). The arithmetic unit of a butterfly processor and a twiddle factor generator are based on a CORDIC algorithm. An efficient implementation of the CORDIC-based split-radix FFT algorithm is demonstrated. The chip of 2048/4096/8192-point FFT/IFFT core processor is fabricated in a 0.18 µm CMOS technology. The core size is 4860×7883 µm2 and contains about 200 822 gates for logic and memory, and the power dissipation is 350 mW with a clock rate of 150 MHz at 1.8 V. All control signals are generated internally on-chip. The processor performs 8192-point FFT/IFFT every 138 µs and 2048-point FFT/IFFT every 34.5 µs, respectively, which exceeds orthogonal frequency division multiplexer symbol rates. The modified-pipelining CORDIC arithmetic unit is employed for complex multiplication. A CORDIC twiddle factor generator is proposed and implemented for reducing the size of ROM required for storing the twiddle factors. Compared with conventional FFT implementations, the power consumption is reduced by 25%.