A Low-Area, 0.18μm CMOS, 10Gb/s Optical Receiver Analog Front End

Abstract

A fully integrated, low-cost (area), low-power, high-gain, differential optical receiver analog front-end (AFE), including transimpedance amplifier (TIA), limiting amplifier (LA), DC-offset cancellation feedback and output-buffer is designed in TSMC 0.18μm CMOS technology. The optimized TIA has a regulated cascode (RGC) topology, with 5.9mW power-dissipation, 48 dBΩ gain, 8.46GHz bandwidth. The proposed limiting amplifier (LA) has an inductor-less topology, with 41.9dB gain, 91.1mW power consumption (including output buffer), output swing of 0.4V _p-p , and bandwidth of 7.88GHz (output-buffer applied), using built-in active inductors and negative Miller capacitance to broaden the bandwidth. The AFE has 89.94 dBΩ gain, 6.84GHz bandwidth, 0.4V _p-p output voltage swing to 50Ω transmission lines, 103.2mW power consumption with 1.8V supply voltage, and sensitivity of 14.5μA for BER of 10 ^-12 .