Parallel implementation of fractal image compression

Abstract

This paper presents an implementation of fractal image compression on a Texas Instruments TMS320C80 parallel processor chip. The work focuses on improving encoding speed. Speed gains are nearly linearly related to the number of processors used. An approach for reducing the number of calculations made, based on the variance of pixel values over sub-blocks of the image is presented. The various techniques employed allow a 512/spl times/512 pixel 256 grey-level image to be compressed in under 20 seconds, while maintaining peak signal to noise ratios of close to 30 dB. This paper also describes an extension of this work to allow colour images to be compressed.